1. Field of the Invention
The present invention relates to a storage unit and a storage device, particularly to a non-volatile storage unit and a non-volatile storage device.
2. Description of the Prior Art
The programmable logic device (PLD) is a programmable and reprogrammable configuration element. The logic functions and/or related route paths of PLD can be programmed or reprogrammed via writing new data to the configuration elements. It should be further annotated: PLD is also called the programmable array logic (PAL), the programmable logic array (PLA), the field programmable gate array (FPGA) or other devices with similar functions.
The conventional configuration elements of PLD are normally realized with 6-transistor static random access memories (6T SRAM). It is well known by the persons skilled in the art: the 6T SRAM is likely to be affected by soft errors. The probability of soft errors increases with the decrease of the element size or the decrease of the voltage applied to the elements. Further, SRAM is a volatile memory into which configuration data needs to be loaded while initializing a PLD, and that, therefore, consumes a longer period of time.
The content addressable memory (CAM) can be used to compare the input data and the data stored in SRAM and output the result of comparison. CAM may also suffer the same defect as SRAM. A current solution to the abovementioned problem is using memristors to replace SRAM. In order to meet the layout design rule, appropriate spacing should be reserved for two adjacent memristors (such as phase-change memories). Thus, a memristor-based memory would occupy a larger area in a chip.
Accordingly, it is highly desirable to propose a compact-layout non-volatile storage device applicable to PLD and CAM.